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ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 256mb f-die ddr sdram specification revision 1.3 october, 2004
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 256mb f-die revision history revision 1.0 (june, 2003) - first version for internal review revision 1.1 (agust, 2003) - added x8 org (k4h560838f) and speed aa revision 1.2 (may, 2004) - modified idd current spec. revision 1.3 (october, 2004) - corrected typo.
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 ? double-data-rate arch itecture; two data transfers per clock cycle ? bidirectional data strobe l(u)dqs ? four banks operation ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? mrs cycle with address key programs -. read latency 2, 2.5 (clock) -. burst length (2, 4, 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive go ing edge of the system clock(ck) ? data i/o transactions on both edges of data strobe ? edge aligned data output, center aligned data input ? ldm,udm for write masking only (x16) ? auto & self refresh ? 7.8us refresh interv al(8k/64ms refresh) ? maximum burst refresh cycle : 8 ? 66pin tsop ii package ordering information part no. org. max freq. interface package k4h561638f-tc/lb3 16m x 16 b3(ddr333@cl=2.5) sstl2 66pin tsop ii k4h561638f-tc/laa aa(ddr266@cl=2) k4h561638f-tc/la2 a2(ddr266@cl=2) k4h561638f-tc/lb0 b0(ddr266@cl=2.5) k4h560838f-tc/lb3 32m x 8 b3(ddr333@cl=2.5) sstl2 66pin tsop ii k4h560838f-tc/laa aa(ddr266@cl=2) k4h560838f-tc/la2 a2(ddr266@cl=2) k4h560838f-tc/lb0 b0(ddr266@cl=2.5) key features *cl : cas latency operating frequencies b3(ddr333@cl=2.5) aa(ddr266@cl=2.0) a2(ddr266@cl=2.0) b0(ddr266@cl=2.5) speed @cl2 133mhz 133mhz 133mhz 100mhz speed @cl2.5 166mhz 133mhz 133mhz 133mhz
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 pin description dm is internally loaded to match dq and dqs identically. 256mb tsop-ii package pinout row & column address configuration 1 66pin tsop ii (400mil x 875mil) 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 54 53 52 51 50 49 48 47 46 45 44 43 35 36 37 38 39 40 41 42 55 56 57 58 59 60 34 (0.65mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 bank address ba0~ba1 auto precharge a10 organization row address column address 32mx8 a0~a12 a0-a9 16mx16 a0~a12 a0-a8 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc nc nc v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc a 12 16mb x 16 32mb x 8 v dd dq 0 v ddq nc dq 1 v ssq nc dq 2 v ddq nc dq 3 v ssq ba 0 cs ras cas we nc v ddq nc v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc nc nc nc nc v dd v ss dq 7 v ssq nc dq 6 v ddq nc dq 5 v ssq nc dq 4 v ddq a 11 cke ck dm v ref v ssq nc v ss a 4 a 5 a 6 a 7 a 8 a 9 nc dqs nc v ss ck nc a 12
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 units : millimeters 0.30 0.08 0.65typ (0.71) 22.22 0.10 0.125 (0.80) 10.16 0.10 0 ~8 #1 #33 #66 #34 (1.50) (1.50) 0.65 0.08 1.00 0.10 1.20max (0.50) (0.50) (10.16) 11.76 0.20 (10 ) (10 ) +0.075 -0.035 (0.80) 0.10 max 0.075 max [] 0.05 min (10 ) (10 ) ( r 0 . 1 5 ) 0.210 0.05 0.665 0.05 (r0.15) ( 4 ) ( r 0 . 2 5 ) (r0.25) 0.45~0.75 0.25typ note 1. ( ) is reference 2. [ ] is ass ? y out quality 66pin tsopii / package dimension package physical dimension
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 4mx16 / 2mx32 4mx16 / 2mx32 4mx16 / 2mx32 4mx16 / 2mx32 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register dll strobe gen. ck, ck add lcke ck, ck cke cs ras cas we ck, ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck x16/x32 x6/x32 x8/x16 x8/x16 lwe x8/x16 dqi data strobe block diagram ( 8mbit x 8 / 4mbit x 16 i/o x 4 banks) l(u)dm l(u)dm dm input register
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sam- pled on the positive edge of ck and negative edge of ck . output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. de activating the clock provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously . input buffers, excluding ck, ck and cke are disabled dur- ing power-down and self refresh modes, providing low standby power. cke will recognize an lvcmos low level prior to vref being stable on power-up. cs input chip select : cs enables(registered low) and disabl es(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. l(u)dm input input data mask : dm is an input mask signal for write data. input dat a is masked when dm is sampled high along with that input data dur ing a write access. dm is sampled on both edges of dqs. although dm pins are input onl y, the dm loading matches the dq and dqs loading. ldm corresponds to the data on dq0~d7 ; udm corresponds to the data on dq8~dq15. dm may be driven high, low, or floating during reads. ba0, ba1 input bank addres inputs : ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a [0 : 12] input address inputs : provide the row address fo r active commands, and the column address and auto precharge bit for read/write commands , to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode regist er set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). dq i/o data input/output : data bus l(u)dqs i/o data strobe : output with read data, input wi th write data. edge-aligned with read data, cen- tered in write data. used to capture wr ite data. ldqs corresponds to the data on dq0~d7 ; udqs corresponds to the data on dq8~dq15 nc - no connect : no internal el ectrical connection is present. vddq supply dq power supply : +2.5v 0.2v. vssq supply dq ground. vdd supply power supply : +2.5v 0.2v (device specific). vss supply ground. vref input sstl_2 reference voltage. input/output function description
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9, a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll l h x 3 self refresh entry l 3 exit l h lh h h x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv v v exit l h x x x x precharge power down mode entry h l hx x x x lh h h exit l h hx x x lv v v l(u)dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh h h 9 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/mrs can be issued onl y at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are sa me as the cbr refresh of dram. the automatical precharge without ro w precharge command is meant by "auto". auto/self refresh can be iss ued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, writ e, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row acti ve and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row ac tive and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row ac tive and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. udm/ldm sampled at the rising and falling edges of the udqs/ldqs and data-in are masked at the both edges (write udm/ldm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. note :
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 8m x 8bit x 4 banks / 4m x 16bit x 4 banks double data rate sdram the k4h560838f / k4h561638f is 268,435,456 bits of double data rate synchronous dram organized as 4x 8,388,608 / 4x 4,194,304 words by 4/16bits, fabricated with samsung s high performance cmos technology. synchr onous features with data strobe allow extremely high performance up to 333mb/s per pin. i/o transactions are possible on both edges of dqs. range of operating freque n- cies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memo ry system applications. general description absolute maximum rating parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd & v ddq supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 w short circuit current i os 50 ma note : permanent device damage may occur if absolute maximum rating are exceeded. functional operation should be restri cted to recommend operation condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. dc operating conditions recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 1.vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on vref ma y not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the diff erence between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is specified for the same temperat ure and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. fo r a given output, it represents t he maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to s ource voltages from 0.1 to 1.0. note :
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 ddr sdram spec items & test conditions conditions symbol operating current - one bank active-precharge; trc=trcmin; tck=10ns for ddr200, 7.5ns for ddr266, 6ns for ddr333; dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. idd0 operating current - on e bank operation ; one bank open, bl=4, reads - refer to the following page for detailed test condition idd1 percharge power-down standby current; all banks idle; power - down mode; cke = =vih(min);all banks idle; cke > = vih(min); tck=10ns for ddr200, 7.5ns for ddr266, 6ns for ddr333 ; address and other control inputs changing once per clock cycle; vin = vref for dq,dqs and dm idd2f precharge quiet standby current; cs# > = vih(min); all banks idle; cke > = vih(min); tck=10ns for ddr 200, 7.5ns for ddr266, 6ns for ddr 333; address and other control inputs stable at >= vih(min) or == vih(min); cke>=vih(min); one bank active; active - precharge; trc=trasmax; tck=10ns for ddr200, 7.5ns for ddr266, 6ns for ddr333; dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n operating current - burst read; burst length = 2; reads; continguous burst ; one bank active; address and control inputs changing once per clock cycle; cl=2 at tck=10ns for ddr200, cl=2 at 7.5ns for ddr266(a2), cl=2.5 at 7.5ns for ddr266(b0), 6ns for ddr333; 50% of data changing on every transfer; lout = 0 m a idd4r operating current - burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; cl=2 at tc k= 10ns for ddr200, cl=2 at tck=7.5ns for ddr266(a2), cl=2.5 at tck=7.5ns for ddr266(b0), 6ns for ddr333; dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every burst idd4w auto refresh current; trc = trfc(min) - 8*tck for ddr200 at tck=10ns; 10*tck for dd r266 at tck=7.5ns; 12*tck for ddr333 at tck=6ns; distributed refresh idd5 self refresh current; cke =< 0.2v; external clock on; tck = 10ns for ddr200, tck=7.5ns for ddr266, 6ns for ddr333. idd6 orerating curren t - four bank operation ; four bank interleaving with bl=4 -refer to the following page for detailed test condition idd7a input/output capacitance (v dd =2.5, v ddq =2.5v, t a = 25 c, f=1mhz) parameter symbol min max delta unit note input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras ,cas , we ) cin1 2 3 0.5 pf 4 input capacitance( ck, ck ) cin2 2 3 0.25 pf 4 data & dqs input/output capacitance cout 4 5 0.5 pf 1,2,3,4 input capacitance(udm/ ldm) cin3 4 5 pf 1,2,3,4 1.these values are guaranteed by design and are tested on a sample basis only. 2. although dm is an input -only pin, the i nput capacitance of this pin must model t he input capacitance of the dq and dqs pin s. this is required to match signal propagat ion times of dq, dqs, and dm in the system. 3. unused pins are tied to ground. 4. this parameteer is sampled. vddq = +2.5v +0.2 v, vdd = +3.3v +0.3v or +0.25v+0.2v, f=100mhz, ta=25 c, vout(dc) = vddq/2, vout(peak to peak) = 0.2v. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loadi ng (to facilitate trace matching at the board level). note :
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 idd7a : operating curren t: four bank operation 1. typical case : vdd = 2.5v, t=25? c 2. worst case : vdd = 2.7v, t= 10? c 3. four banks are being interleaved with trc(min) , burst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - b0(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *50% of data changing at every burst - a2(133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3* tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *50% of data changing at every burst - aa (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4 , trcd = 2*tck, trc = 8*tck, tras = 6*tck read : a0 n r0 n n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - b3(166mhz,cl=2.5) : tck=6ns, cl=2.5, bl=4, trrd=2*tck, trcd=3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop < detailed test conditions for ddr sdram idd1 & idd7a > idd1 : operating curren t: one bank operation 1. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 2. timing patterns - b0(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl =4, trcd = 3*tck, trc = 9*tck, tras = 6*tck read : a0 n n r0 n n p0 n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - a2 (133mhz, cl=2) : tck = 7.5ns, cl=2, bl =4, trcd = 3*tck, trc = 9*tck, tras = 6*tck read : a0 n n r0 n n p0 n n a0 n - r epeat the same timing with random address changing *50% of data changing at every burst - aa (133mhz, cl=2) : tck = 7.5ns, cl=2, bl =4, trcd = 2*tck, trc = 8*tck, tras = 6*tck read : a0 n r0 n n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - b3(166mhz, cl=2.5) : tck=6ns, cl=2.5, bl=4, trcd=3*tck, trc = 10*tck, tras=7*tck read : a0 n n r0 n n p0 n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 ddr sdram i dd spec table (v dd =2.7v, t = 10 c) symbol 32mx8 (k4h560838f) unit notes b3(ddr333@cl=2.5) aa(ddr266@cl=2.0) a2(ddr266@cl=2.0) b0(ddr266@cl=2.5) idd0 90 90 80 ma idd1 115 115 105 ma idd2p 3 3 3 ma idd2f 30 25 25 ma idd2q 25 23 23 ma idd3p 35 30 30 ma idd3n 55 45 45 ma idd4r 160 140 140 ma idd4w 160 135 135 ma idd5 170 160 160 ma idd6 normal 3 3 3 ma low power 1.5 1.5 1.5 ma optional idd7a 280 280 250 ma symbol 16mx16 (k4h561638f) unit notes b3(ddr333@cl=2.5) aa(ddr266@cl=2.0) a2(ddr266@cl=2.0) b0(ddr266@cl=2.5) idd0 90 90 80 ma idd1 125 115 115 ma idd2p 3 3 3 ma idd2f 30 25 25 ma idd2q 25 23 23 ma idd3p 35 30 30 ma idd3n 55 45 45 ma idd4r 200 170 170 ma idd4w 190 165 165 ma idd5 180 165 165 ma idd6 normal 3 3 3 ma low power 1.5 1.5 1.5 ma optional idd7a 350 300 300 ma
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 ac operating conditions parameter/condition symbol min max-10 unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v input differential voltage, ck and /ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and /ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 ac overshoot/undershoot specification for address and control pins parameter specification ddr333 ddr200/266 maximum peak amplitude allowed for overshoot 1.5 v 1.5 v maximum peak amplitude allowed for undershoot 1.5 v 1.5 v the area between the overshoot signal and vdd must be less than or equal to 4.5 v-ns 4.5 v-ns the area between the undershoot signal and gnd must be less than or equal to 4.5 v-ns 4.5 v-ns 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 0.6875 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.3125 6.5 7.0 vdd overshoot maximum amplitude = 1.5v area = 4.5v-ns maximum amplitude = 1.5v undershoot gnd volts (v) tims(ns) ac overshoot/undershoot definition notes : 1. vid is the magnitude of the difference between the input le vel on ck and the input level on /ck. 2. the value of vix is expected to equal 0. 5*vddq of the transmitting device and must tr ack variations in the dc level of the s ame.
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 overshoot/undershoot specification for data, strobe, and mask pins parameter specification ddr333 ddr200/266 maximum peak amplitude allowed for overshoot 1.2 v 1.2 v maximum peak amplitude allowed for undershoot 1.2 v 1.2 v the area between the overshoot signal and vdd must be less than or equal to 2.4 v-ns 2.4 v-ns the area between the undershoot signal and gnd must be less than or equal to 2.4 v-ns 2.4 v-ns 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 vddq overshoot maximum amplitude = 1.2v area = 2.4v-ns maximum amplitude = 1.2v undershoot gnd volts (v) tims(ns) dq/dm/dqs ac overshoot/undershoot definition
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 ac timming parameters & specifications parameter symbol b3 (ddr333@cl=2.5) aa (ddr266@cl=2.0) a2 (ddr266@cl=2.0) b0 (ddr266@cl=2.5) unit note min max min max min max min max row cycle time trc 60 60 65 65 ns refresh row cycle time trfc 72 75 75 75 ns row active time tras 42 70k 45 120k 45 120k 45 120k ns ras to cas delay trcd 18 15 20 20 ns row precharge time trp 18 15 20 20 ns row active to row active delay trrd 12 15 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read commandtwtr1111tck col. address to col. address delaytccd1111tck clock cycle time cl=2.0 tck 7.5127.5127.512 10 12ns cl=2.5 6 12 7.5 12 7.5 12 7.5 12 ns clock high level width tch 0.45 0. 55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck tac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to ouput data edge tdqsq - 0.45 - 0.5 - 0.5 - 0.5 ns 12 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres0000ns3 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control in put setup time(fast) tis 0.75 0.9 0.9 0.9 ns i,5.7 address and control input hold time(fast) tih 0.75 0.9 0.9 0.9 ns i,5.7 address and control in put setup time(slow) tis 0.8 1.0 1.0 1.0 ns i, address and control input hold time(slow) tih 0.8 1.0 1.0 1.0 ns i, data-out high impedence time from ck/ck thz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns 1 data-out low impedence time from ck/ck tlz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns 1 output slew rate matching ratio(rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 system characteristics for ddr sdram the following specification parameters are required in systems using ddr333, ddr266 & ddr200 devices to ensure proper system performance. these characte ristics are for system simulation pu rposes and are guaranteed by design. table 1 : input slew rate fo r dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate ac characteristics ddr333 ddr266 ddr200 parameter symbol min max min max min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 0.5 4.0 0.5 4.0 v/ns a, m input slew rate tis tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate tds tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k parameter symbol b3 (ddr333@cl=2.5)) aa (ddr266@cl=2.0) a2 (ddr266@cl=2.0) b0 (ddr266@cl=2.5)) unit note min max min max min max min max mode register set cycle time tmrd 12 15 15 15 ns dq & dm setup time to dqs tds 0.45 0.5 0.5 0.5 ns j, k dq & dm hold time to dqs tdh 0.45 0.5 0.5 0.5 ns j, k control & address input pulse width tipw 2.2 2.2 2.2 2.2 ns 8 dq & dm input pulse width tdipw 1.75 1.75 1.75 1.75 ns 8 power down exit time tpdex 6 7.5 7.5 7.5 ns exit self refresh to non-read command txsnr 75 75 75 75 ns exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 4 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs -ns11 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -ns10, 11 data hold skew factor tq hs 0.55 0.75 0.75 0.75 ns 11 dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 2 active to read with auto precharge command trap 18 20 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 13
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 table 4 : input/output setup & hold derating for rise/fall delta slew rate table 5 : output slew rate characteristice (x16 devices only) table 6 : output slew rate matching ratio characteristics delta slew rate tds tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr266 ddr200 parameter min max min max notes output slew rate matching ratio (pullup to pulldown) tbd tbd 0.67 1.5 e,m
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 component notes 1. thz and tlz transitions occur in the same access time wi ndows as valid data transitions. t hese parameters are not referenc ed to a specific voltage level but specify when the device output in no longer driving (hz), or begins driving (lz). 2. the maximum limit for this parameter is not a device limit. the device will operat e with a greater value for this paramete r, but sys tem performance (bus turnaround) will degrade accordingly. 3. the specific requirement is that dqs be valid (high, low, or at some poi nt on a valid transition) on or before this ck edg e. a valid transition is defined as monotonic and meeting the input slew rate spec ifications of the dev ice. when no writes we re previ ously in progress on the bus, dqs will be tran sitioning from high- z to logic low. if a previous write was in progress , dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 4. a maximum of eight auto refresh comm ands can be posted to any given ddr sdram device. 5. for command/address input slew rate 1.0 v/ns 6. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns 7. for ck & ck slew rate 1.0 v/ns 8. these parameters guarantee device ti ming, but they are not necessarily test ed on each device. they may be guaranteed by device design or tester correlation. 9. slew rate is measured between voh(ac) and vol(ac). 10. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the mini mum specification limits for tc l and tch).....for example, tcl and tch are = 50% of th e period, less the half period jitt er (tjit(hp)) of the clock source, and less the half period jitter due to crosstalk (tji t(crosstalk)) into the clock traces. 11. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defi ned by clock high or clock low (tch, tcl). tqhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effect s, and p- channel to n-channel variation of the output drivers. 12. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 13. tdal = (twr/t ck) + (trp/tck) for each of the terms above, if not already an integer , round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5ns tdal = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tdal = 5 clocks system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 1. output test point vssq 50 ? figure 1 : pullup slew rate test load
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 b. pulldown slew rate is measured under the test conditions shown in figure 2. output test point vddq 50 ? figure 2 : pulldown sl ew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is meas ured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met fo r any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.5v, typical process minimum : 70 c (t ambient), vddq = 2. 3v, slow - slow process maximum : 0 c (t ambient), vddq = 2. 7v, fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is s pecified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the ma ximum difference between pullup and pulldown drivers due to process variation. f. verified under typical condi tions for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to in crease tis and tih in the case where t he input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesser of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), si milarly for rising transitions. j. a derating factor will be used to increas e tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc del ta rise, input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where the i/o slew rate is bel ow 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew ra te and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rate s deter mined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), and similarly for rising transitions. m. dqs, dm, and dq input slew rate is s pecified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotony.
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 figure 3. i/v characteristics for input/output buffers:pull up(above) and pull down(below) maximum typical high minumum vout(v) iout(ma) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.0 1.0 2.0 minimum typical low typical high maximum 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 iout(ma) typical low vout(v) pullup characteristics for full strength output driver pulldown characteristics for full strength output driver ibis :i/v characteristics for input and output buffers ddr sdram output driver v-i characteristics ddr sdram output driver char acteristics are defined for full and half strength operation as selected by the emrs bit a1. figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 s how the same data in tabular format suitable f or input into simulation tools. the driver c haracteristcs evaluat ion conditions are: output driver characteristic curves notes: 1. the full variation in driver current from minimum to maxi mum process, temperature and volt age will lie within the outer bou nding lines the of the v-i curve of figure 3 and 4. 2. it is recommended that the "typical" ib is v-i curve lie within the inner bounding li nes of the v-i curves of figure 3 and 4. 3. the full variation in the ratio of the "typical" ibis pullup to "typical" ibis pulldown current should be unity +/- 10%, for device drain to source voltages from 0.1 to1.0. this specif ication is a design objective only. it is not guaranteed. typical 25c vdd/vddq = 2.5v, typical process minimum 70c vdd/vddq = 2.3v, slow-slow process maximum 0c vdd/vddq = 2.7v, fast-fast process
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 pulldown current (ma) pullup current (ma) voltage (v) typical low typical high minimum maximum typical low typical high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -41.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 - 51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 - 51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 - 51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 - 51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 - 51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 - 51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 - 52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 - 52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 - 52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 - 52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 - 52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 - 52.8 -160.1 -41.2 -198.2 table 7. full strength driver characteristics
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 figure 4. i/v characteristics for input/output buffers:pull up(above) and pull down(below) maximum typical high minumum vout(v) iout(ma) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 1.0 2.0 iout(ma) minimum typical low typical high maximum 0 10 20 30 40 50 60 70 80 90 0.0 1.0 2.0 iout(ma) typical low vout(v) pullup characteristics for weak output driver pulldown characteristics for weak output driver
ddr sdram ddr sdram 256mb f-die (x8, x16) rev. 1.3 october, 2004 pulldown current (ma) pullup current (ma) voltage (v) typical low typical high minimum maximum typical low typical high minimum maximum 0.1 3.4 3.8 2.6 5.0 - 3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 - 6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7 table 8. weak driver characteristics

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